The present invention pertains to power consumption in a processor front end. More particularly, the present invention relates to reducing power consumption due to cache and TLB accesses in a processor front-end.
A processor is a computing device that executes instructions to operate upon data in a computer system. A processor implemented on a single-chip is sometimes referred to as a xe2x80x9cmicroprocessorxe2x80x9d. The data and instructions used by a processor are generally stored in memory. The circuitry responsible for fetching and decoding instructions is often referred to as the xe2x80x9cfront endxe2x80x9d of the processor. One problem associated with many processors is that of reducing or limiting power consumption in the processor. This problem is becoming increasingly more difficult to solve as processor clock speeds increase and as the number of transistors used to implement processors increase.
Many modern processors include one or more cache memories to allow faster access to frequently used instructions and data. Commonly, such caches include both an instruction cache and a data cache. A cache normally includes a tag array containing the address tags of cached information and a data array containing the cached information. Each time data is fetched from the cache, power is consumed. Accesses to an instruction cache, therefore, contribute to the overall power consumption in the processor front end.
A processor which uses virtual addressing may also include a translation look-aside buffer (TLB). The TLB contains a mapping (e.g., a look-up table) of virtual addresses to physical addresses. The mapping is commonly divided into units of memory called xe2x80x9cpagesxe2x80x9d. Each time a look-up is made to the TLB, power is consumed. Hence, accesses to an instruction TLB also contribute to the overall power consumption in the processor front end.
Despite the fact that code flow is often linear (incremental, or sequential), existing processors will continually perform look-ups to the tag array and data array of the instruction cache, and to the TLB, even if the entry being accessed is not changing. The reason for this is that the instruction fetch size is less than an entire cache line or, in the case of the TLB, less than an entire page. This approach may be dictated by the instruction queue topology, cache line size, instruction width, routing limitations, etc., however, it also has a wasteful effect on power usage. A potential solution to this problem is to increase the instruction fetch size. That approach might provide some benefit, however, as the fetch size increases, the chances of fetching unneeded code (due to spatial locality) increases, and again power can be wasted. Also, increasing the fetch size can increase bus widths and cache area costs. Hence, a better solution to reducing power consumption in a processor front end due to instruction cache and TLB accesses is needed.